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INTEGRATED CIRCUITS
DATA SHEET
P83CL781; P83CL782 Low voltage 8-bit microcontrollers with UART and I2C-bus
Product specification Supersedes data of 1995 Jul 13 File under Integrated Circuits, IC20 1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 12 12.1 12.2 12.3 12.4 12.5 13 13.1 13.2 13.3 13.4 FEATURES GENERAL DESCRIPTION APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION OVERVIEW General CPU timing MEMORY ORGANIZATION Program memory Data memory Special Function Registers Addressing I/O FACILITIES Ports Port options Port 0 options SET/RESET options TIMER/EVENT COUNTERS Timer 0 and Timer 1 Timer T2 Timer/Counter 2 Control Register (T2CON) REDUCED POWER MODES Idle mode Power-down mode Wake-up from Power-down mode Status of external pins Power Control Register (PCON) I2C-BUS SERIAL I/O Serial Control Register (S1CON) Serial Status Register (S1STA) Data Shift Register (S1DAT) Address Register (S1ADR) 14.3 15 15.1 15.2 15.3 16 17 17.1 17.2 18 19 20 21 22 22.1 22.2 23 24 24.1 24.2 24.3 25 26 27 14 14.1 14.2
P83CL781; P83CL782
STANDARD SERIAL INTERFACE SIO0: UART
Multiprocessor communications Serial Port Control and Status Register (S0CON) Baud rates INTERRUPT SYSTEM External interrupts INT2 to INT9 Interrupt priority Interrupt registers OSCILLATOR CIRCUITRY RESET External reset using the RST pin Power-on reset SPECIAL FUNCTION REGISTERS OVERVIEW INSTRUCTION SET LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS Program memory External Data Memory PACKAGE OUTLINES SOLDERING Introduction DIP QFP DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Mar 14
2
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
1 FEATURES 2
P83CL781; P83CL782
GENERAL DESCRIPTION
* Full static 80C51 CPU * 8-bit CPU, ROM, RAM, I/O in a 40-lead DIP or 44-lead QFP package * 16 kbytes ROM, expandable externally to 64 kbytes * 256 bytes RAM, expandable externally to 64 kbytes * Four 8-bit ports, 32 I/O lines * Three 16-bit timer/event counters * External memory expandable up to 128 kbytes: RAM up to 64 kbytes and ROM up to 64 kbytes * On-chip oscillator suitable for RC, LC, quartz crystal or ceramic resonator * Fifteen source, fifteen vector interrupt structure with two priority levels * Full duplex serial port (UART) * I2C-bus interface for serial transfer on two lines * Enhanced architecture with: - non-page oriented instructions - direct addressing - four 8 byte RAM register banks - stack depth limited only by available internal RAM (maximum 256 bytes) - multiply, divide, subtract and compare instructions * Reduced power consumption through Power-down and Idle modes * Wake-up via external interrupts at Port 1 * Single supply voltage of 1.8 to 6.0 V * Operating ambient temperature: - 83CL781: -40 to +85 C - 83CL782: -25 to +55 C. * Frequency range of DC to 12 MHz * Very low current consumption.
The term P83CL78x is used throughout this data sheet to refer to both the P83CL781 and P83CL782; differences between the devices are highlighted in the text. The P83CL78x is manufactured in an advanced CMOS technology. The P83CL78x has the same instruction set as the 80C51, consisting of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. The device has low power consumption and a wide range of supply voltage; there are two software-selectable modes of reduced activity for further power reduction: Idle and Power-down. For emulation purposes, the P85CL781 (piggy-back version) with 256 bytes of RAM is recommended. The P83CL782 is a faster version of the P83CL781 and operates at a maximum frequency of 12 MHz at VDD 3.1 V. This data sheet details the specific properties of the P83CL78x. For details of the 80C51 core and the I2C-bus see "Data Handbook IC20". 3 APPLICATIONS
The P83CL78x is an 8-bit general purpose microcontroller especially suited for cordless telephone applications. The P83CL78x also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
4 ORDERING INFORMATION TYPE NUMBER(1) NAME P83CL781HFP P83CL782HDP P83CL781HFH P83CL782HDH P83CL781HFH P83CL781HDH Note QFP44 QFP44 DIP40 PACKAGE DESCRIPTION
P83CL781; P83CL782
VERSION SOT129-1 SOT205-1 SOT307-2
plastic dual in-line package; 40 leads (600 mil) plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
1. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program.
1997 Mar 14
4
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
5 BLOCK DIAGRAM
P83CL781; P83CL782
handbook, full pagewidth
T0
3
T1
3
INT0
3
INT1
3
MLA601
XTAL1 TWO 16-BIT TIMER/ EVENT COUNTERS (T0, T1) PROGRAM MEMORY CPU 16 kbyte ROM DATA MEMORY 256 byte RAM
VDD
XTAL2
EA
ALE
PSEN
80C51 core excluding ROM/RAM
WR
3
8-bit internal bus
RD
3
P83CL781 P83CL782
RST
AD0 to 7
0
A8 to 15
2
PARALLEL I/O PORTS AND EXTERNAL BUS
SERIAL UART PORT
16-BIT TIMER/ EVENT COUNTER
I2 C INTERFACE
V SS
3
3
1
1
1
1
P0 P1 P2 P3
0 alternative function of Port 0 1 alternative functions of Port 1
TXD RXD
T2
T2EX
SCL
SDA
2 alternative function of Port 2 3 alternative function of Port 3
Fig.1 Block diagram.
1997 Mar 14
5
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
6 FUNCTIONAL DIAGRAM
P83CL781; P83CL782
handbook, full pagewidth
XTAL1 LOW ORDER ADDRESS AND DATA BUS (AD0 to AD7)
XTAL2 PORT 0 EA PSEN ALE
T2 T2EX
PORT 1
SCL SDA
INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9
P83CL781 P83CL782
PORT 2
HIGH ORDER ADDRESS BUS (A8 to A15)
RXD/data TXD/clock INT0 INT1 T0 T1 WR RD
PORT 3
RST
VSS VDD
MBH885
Fig.2 Functional diagram.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
7 7.1 PINNING INFORMATION Pinning
P83CL781; P83CL782
P1.0/INT2/T2 P1.1/INT3/T2EX P1.2/INT4 P1.3/INT5 P1.4/INT6 P1.5/INT7 P1.6/INT8/SCL P1.7/INT9/SDA RST
1 2 3 4 5 6 7 8 9 P83CL781 P83CL782
40 39 38 37 36
V DD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
35 P0.4/AD4 34 P0.5/AD5 33 32 31 P0.6/AD6 P0.7/AD7 EA
P3.0/RXD/data 10 P3.1/TXD/clock 11 P3.2/INT0 12 P3.3/INT1 13 P3.4/T0 14 P3.5/T1 15 P3.6/WR 16 P3.7/RD 17 XTAL2 XTAL1 V SS 18 19 20
30 ALE 29 PSEN
28 P2.7/A15 27 P2.6/A14
26 P2.5/A13 25 P2.4/A12
24 P2.3/A11 23 P2.2/A10
22 P2.1/A9 21 P2.0/A8
MLA603
Fig.3 Pin configuration for DIP40 package.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
P1.1/INT3/T2EX
44 P1.4/INT6
43 P1.3/INT5
42 P1.2/INT4
P1.0/INT2/T2
37 P0.0/AD0
36 P0.1/AD1
35 P0.2/AD2
P1.5/INT7 P1.6/INT8/SCL P1.7/INT9/SDA RST P3.0/RXD/data n.c. P3.1/TXD/clock P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1
1 2 3 4 5 6 7 8 9 10 11
34 P0.3/AD3
38 VDD
41
40
39
n.c.
33 32 31 30 29
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA n.c. ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
P83CL781 P83CL782
28 27 26 25 24 23
MLA604
20
21 P2.3/A11
P3.6/WR 12
P3.7/RD 13
XTAL2 14
XTAL1 15
VSS 16
TEST/V SS 17
P2.0/A8 18
P2.1/A9 19
P2.2/A10
Fig.4 Pin configuration for QFP44 packages.
1997 Mar 14
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P2.4/A12
22
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
7.2 Pin description PIN SYMBOL DIP40 P1.0/INT2/T2 P1.1/INT3/T2EX P1.2/INT4 P1.3/INT5 P1.4/INT6 P1.5/INT7 P1.6/INT8/SCL P1.7/INT9/SDA RST n.c. P3.0/RXD/data P3.1/TXD/clock P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 QFP44 40 41 42 43 44 1 2 3 4 6 5 7 8 9 10 11 12 13
P83CL781; P83CL782
DESCRIPTION * Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that have logic 1s written to them are pulled HIGH by internal pull-ups, and in this state can be used as inputs (note that P1.6 and P1.7 are open-drain only). As inputs, Port 1 pins that are externally pulled LOW will source current (IIL) due to the internal pull-ups. Port 1 output buffers can sink/source 4 LS TTL loads. * Alternative functions: - INT2 to INT9 are external interrupt inputs - T2 and T2EX are the Timer/event counter 2 inputs - SCL and SDA are the I2C-bus clock and data lines. Reset: A HIGH level on this pin for two machine cycles while the oscillator is running, resets the device. Not connected. * Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7). Same characteristics as Port 1. * Alternative functions: - RXD/data is the UART serial data input (asynchronous) or data I/O (synchronous) - TXD/clock is the UART serial data output (asynchronous) or clock output (synchronous) - INT0 and INT1 are external interrupt lines - T0 and T1 are external inputs for Timer 0 and Timer 1 respectively - WR is the external memory write strobe and RD is the external memory read strobe.
XTAL2 XTAL1 VSS TEST/VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15
18 19 20 - 21 22 23 24 25 26 27 28
14 15 16 17 18 19 20 21 22 23 24 25
Crystal Output: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external oscillator clock is used. Crystal Input: Input to the inverting amplifier that forms the oscillator, also the input for an externally generated clock source. Ground: Circuit ground potential. Test Input: Must be connected to VSS or left open. * Port 2: 8-bit bidirectional I/O port (P2.0 to P2.7). Same characteristics as Port 1. * High-order addressing: A8 to A15 make up the high-order address byte during accesses to external memory that use 16-bit addresses (MOVX@DPTR). In this application the pins use the strong internal pull-ups when emitting logic 1's. During accesses to external memory that use 8-bit addresses (MOVX@Ri), the pins emit the contents of the P2 Special Function Register.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
PIN SYMBOL DIP40 PSEN 29 QFP44 26
P83CL781; P83CL782
DESCRIPTION Program Store Enable: Read strobe to external Program Memory. When executing code out of external Program Memory, PSEN is activated twice each machine cycle. However, during each access to external Data Memory two PSEN activations are skipped. Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods and may be used for external timing or clocking purposes. Not connected. External Access: When EA is held HIGH, the CPU executes out of the internal Program Memory (unless the Program Counter exceeds 3FFFH). When EA is held LOW, the CPU executes out of external Program Memory regardless of the value of the program counter. * Port 0: 8-bit open-drain bidirectional I/O port (P0.7 to P0.0). As an open-drain output port it can sink/source 8 LS TTL loads. Port 0 pins that have logic 1s written to them float, and in this state will function as high-impedance inputs. * Low-order addressing: AD7 to AD0 provide the multiplexed low-order address and data bus during accesses to external memory. In this application the pins use the strong internal pull-ups when emitting logic 1s.
ALE
30
27
n.c. EA
- 31
28 29
P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD n.c.
32 33 34 35 36 37 38 39 40 -
30 31 32 33 34 35 36 37 38 39
Power supply. Not connected.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
8 FUNCTIONAL DESCRIPTION OVERVIEW
P83CL781; P83CL782
The device has two software-selectable modes of reduced activity for power reduction: * Idle mode; freezes the CPU while allowing the timers, serial I/O and interrupt system to continue functioning. * Power-down mode; saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. In addition, two serial interfaces are provided on-chip: * a standard UART serial interface, and * a standard I2C-bus serial interface. The I2C-bus serial interface has byte-oriented master and slave functions allowing communication with the whole family of I2C-bus compatible devices. 8.2 CPU timing
This chapter gives a brief overview of the device. The detailed functional description is in the following chapters: Chapter 9 "Memory organization" Chapter 10 "I/O facilities" Chapter 11 "Timer/event counters" Chapter 12 "Reduced power modes" Chapter 13 "I2C-bus serial I/O" Chapter 14 "Standard serial interface SIO0: UART" Chapter 15 "Interrupt system" Chapter 16 "Oscillator circuitry" Chapter 17 "Reset". 8.1 General
The P83CL78x is a stand-alone high-performance CMOS microcontroller designed for use in real-time applications such as instrumentation, industrial control, intelligent computer peripherals and consumer products. The device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 64 kbytes of Program Memory and/or up to 64 kbytes of data storage. The P83CL78x contains a non-volatile 16 kbyte read-only Program Memory; a static 256 byte read/write Data Memory; 32 I/O lines; three 16-bit timer/event counters; a fifteen-source, two priority-level, nested interrupt structure and on-chip oscillator and timing circuit.
A machine cycle consists of a sequence of 6 states. Each state lasts for two oscillator periods, thus a machine cycle takes 12 oscillator periods or 1 s if the oscillator frequency (fosc) is 12 MHz.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
9 MEMORY ORGANIZATION 9.4 Addressing
P83CL781; P83CL782
The P83CL78x has a 16 kbyte Program Memory (ROM) plus 256 bytes of Data Memory (RAM) on-chip. The device has separate address spaces for Program and Data Memory (see Fig.6). Using Ports P0 and P2, the P83CL78x can address up to 128 kbytes of external memory. The CPU generates both read (RD) and write (WR) signals for external Data Memory accesses, and the read strobe (PSEN) for external Program Memory. 9.1 Program memory
The P83CL78x has five methods for addressing source operands: * Register * Direct * Register-indirect * Immediate * Base-register plus index-register-indirect. The first three methods can be used for addressing destination operands. Most instructions have a `destination/source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand.
The P83CL78x contains 16 kbytes of internal ROM. After reset the CPU begins execution at location 0000H. The lower 16 kbytes of Program Memory can be implemented in either on-chip ROM or external memory. If the EA pin is strapped to VDD, then Program Memory fetches from addresses 0000H through to 3FFFH are directed to the internal ROM. Fetches from addresses 4000H through to FFFFH are directed to external ROM. Program Counter values greater than 3FFFH are automatically addressed to external memory regardless of the state of the EA pin. 9.2 Data memory
alfpage
7FH
30H 2FH bit-addressable space (bit addresses 0 to 7F)
The P83CL78x contains 256 bytes of internal RAM and 34 Special Function Registers (SFRs). The memory map (Fig.6 ) shows the internal Data Memory space divided into the lower 128 bytes, the upper 128 bytes and the SFR space. Internal RAM locations 0 to 127 are directly and indirectly addressable. Internal RAM locations 128 to 255 are only indirectly addressable. The Special Function Register locations 128 to 255 bytes are only directly addressable. 9.3 Special Function Registers
R7 R0 R7 R0 R7 R0 R7 R0
20H 1FH 18H 17H 10H 0FH 08H 07H 0 4 banks of 8 registers (R0 to R7)
The upper 128 bytes are the address locations of the Special Function Registers. Figures 7 and 8 show the Special Function Registers space. The SFRs include the port latches, timers, peripheral control, serial I/O registers, and so on. These registers can only be accessed by direct addressing. There are 128 addressable locations in the SFR address space (SFRs with addresses divisible by eight).
MLA560 - 1
Fig.5 The lower 128 bytes of internal RAM.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
Access to memory addressing is as follows: * Registers in one of the four register banks through register, direct or register-indirect * 256 bytes of internal data RAM through direct or register-indirect * Special Function Registers through direct * External Data Memory through register-indirect * Program Memory look-up tables through base-register plus index-register-indirect.
P83CL781; P83CL782
The P83CL78x is classified as an 8-bit device since the internal ROM, RAM, Special Function Registers, Arithmetic Logic Unit and external data bus are all 8-bits wide. It performs operations on bit, nibble, byte and double-byte data types. Facilities are available for byte transfer, logic and integer arithmetic operations. Data transfer, logic and conditional branch operations can be performed directly on Boolean variables to provide excellent bit handling.
handbook, full pagewidth
64 kbytes
EXTERNAL
64 kbytes
16 kbytes
16 kbytes
16 kbytes
OVERLAPPED SPACE
INTERNAL (EA = 1)
EXTERNAL (EA = 0)
255 (INDIRECT ONLY) 127 INTERNAL DATA RAM 0
SPECIAL FUNCTION REGISTERS
0
PROGRAM MEMORY
INTERNAL DATA MEMORY
MLA605
EXTERNAL DATA MEMORY
Fig.6 Memory map.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
REGISTER MNEMONIC
BIT ADDRESS
DIRECT BYTE ADDRESS (HEX)
FFH FEH FDH FCH IP1 B FF FE F7 F6 FD F5 FC F4 FB F3 FA F2 F9 F1 F8 F0 F8H F0H EFH EEH EDH ECH EBH EAH IX1 IEN1 ACC S1ADR S1DAT S1STA S1CON PSW DF DE DD DC DB DA D7 D6 D5 D4 D3 D2 D9 D1 D8 D0 EF EE ED EC E7 E6 E5 E4 EB EA E3 E2 E9 E1 E8 E0 E9H E8H E0H DBH DAH D9H D8H D0H CFH TH2 TL2 RCAP2H RCAP2L T2CON CF CE CD CC CB CA C9 C8 CEH CDH CCH CBH CAH C9H C8H SFRs containing directly addressable bits
IRQ1
C7 C6
C5
C4
C3
C2
C1
C0
C0H
MLA606 - 1
Fig.7 Special Function Register memory map (continued in Fig.8).
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
REGISTER MNEMONIC
BIT ADDRESS
DIRECT BYTE ADDRESS (HEX)
IP0 P3 B7
BE BD BC B6 B5 B4
BB BA B3 B2
B9 B1
B8 B0
B8H B0H AFH AEH ADH ACH ABH AAH A9H
IEN0 P2 S0BUF S0CON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0
AF AE AD AC A7 A6 A5 A4
AB AA A3 A2
A9 A1
A8 A0
A8H A0H 99H SFRs containing directly addressable bits
9F 97
9E 96
9D 95
9C 94
9B 93
9A 92
99 91
98 90
98H 90H 8DH 8CH 8BH 8AH 89H
8F
8E
8D
8C
8B
8A
89
88
88H 87H 83H 82H 81H
87
86
85
84
83
82
81
80
80H
MLA607
Fig.8 Special Function Register memory map (continued from Fig.7).
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
10 I/O FACILITIES 10.1 Ports
P83CL781; P83CL782
LOW-to-HIGH transition in the port latch; Fig.9(a). Option 2 Open-drain; quasi-bidirectional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor; Fig.9(b). Option 3 Push-Pull; output with drive capability in both polarities. Under this option, pins can only be used as outputs; Fig.9(c). 10.3 Port 0 options
The P83CL78x has 32 I/O lines treated as 32 individually addressable bits or as four parallel 8-bit ports. To enable a port pin alternative function, the port bit latch in its SFR must contain a logic 1. The alternative functions are detailed below: Port 0 Provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals. Port 1 Used for a number of special functions: * Provides the inputs for the eight external interrupts: INT2 to INT9 * External activation of Timer 2: T2 * The I2C-bus interface: SCL and SDA. Port 2 Provides the high-order address when expanding the device with external Program or Data memory. Port 3 Pins can be configured individually to provide: * External interrupt request inputs: INT1 and INT0 * Timer/counter inputs: T1 and T0 * Control signals to read and write to external memories: RD and WR * UART asynchronous input and output (RXD and TXD); or UART synchronous I/O and clock lines (data and clock).1 Each port consists of a latch (SFRs P0 to P3), an output driver and input buffer. Ports 1, 2 and 3 have internal pull-ups (except P1.6 and P1.7). Figure 9(a) shows that the strong transistor `p1' is turned on for only 2 oscillator periods after a LOW-to-HIGH transition in the port latch. When on, it turns on p3 (a weak pull-up) through the inverter. This inverter and p3 form a latch which holds the logic 1. In Port 0 the pull-up `p1' is only on when emitting logic 1s for external memory access. Writing a logic 1 to a Port 1 bit latch leaves both output transistors switched off so that the pin can be used as an high-impedance input. 10.2 Port options
The definition of port options for Port 0 is slightly different. Two cases are considered. First, access to external memory (EA = 0 or access above the built-in memory boundary) and second, I/O accesses. 10.3.1 EXTERNAL MEMORY ACCESSES
Option 1 True logic 0 and logic 1 are written as address to the external memory (strong pull-up to be used). Option 2 An external pull-up resistor is required for external accesses. Option 3 Not allowed for external memory accesses as the port can only be used as output. 10.3.2 I/O ACCESSES
Option 1 When writing a logic 1 to the port latch, the strong pull-up `p1' will be on for 2 oscillator periods. No weak pull-up exists. Without an external pull-up, this option can be used as a high-impedance input. Option 2 Open-drain; quasi-directional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor. See Fig.9(b). Option 3 Push-Pull; output with drive capability in both polarities. Under this option pins can only be used as outputs. See Fig.9(c). 10.4 SET/RESET options
30 of the 32 port pins (excluding P1.6 and P1.7 with option 2S only) may be individually configured with one of the following options. These options are also shown in Fig.9. Option 1 Standard Port; quasi-bidirectional I/O with pull-up. The strong booster pull-up `p1' is turned on for two oscillator periods after a
Individual mask selection of the post-reset state is available with any of the above pins. The required selection is made by appending `S' or `R' to Options 1, 2, or 3 above. Option R RESET, at reset this pin will be initialized LOW. Option S SET, at reset this pin will be initialized HIGH.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
strong pull-up 2 oscillator periods p1
+5 V
p2 p3 I/O pin
Q from port latch
n
input data read port pin INPUT BUFFER (a) Standard
+5 V
external pull-up Q from port latch I/O pin n
input data read port pin INPUT BUFFER
(b) Open-drain
strong pull-up +5 V
p1 I/O pin Q from port latch n
(c) Push-pull
MGD677
Fig.9 Port configuration options.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
11 TIMER/EVENT COUNTERS The P83CL78x contains three 16-bit timer/event counter registers; Timer 0, Timer 1 and Timer 2 which can perform the following functions: * Measure time intervals and pulse durations * Count events * Generate interrupt requests. In the `Timer' operating mode the register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 112 x fosc. In the `Counter' operating mode, the register is incremented in response to a HIGH-to-LOW transition. Since it takes 2 machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition, the maximum count rate is 124 x fosc. To ensure a given level is sampled, it should be held for at least one complete machine cycle. 11.1 Timer 0 and Timer 1 11.2.1
P83CL781; P83CL782
CAPTURE MODE
Figure 10 shows the Capture mode. Two options in this mode, may be selected by the EXEN2 bit in T2CON: * If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which upon overflowing sets the Timer 2 overflow bit TF2, this may then be used to generate an interrupt. * If EXEN2 = 1, Timer 2 operates as described above but with the additional feature that a HIGH-to-LOW transition at external input T2EX causes the current value in TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively. In addition, the transition at T2EX causes the EXF2 bit in T2CON to be set; this may also be used to generate an interrupt. 11.2.2 AUTO-RELOAD MODE
Figure 11 shows the Auto-reload mode. Also two options in this mode are selected by the EXEN2 bit in T2CON: * If EXEN2 = 0, then when Timer 2 rolls over, it sets the TF2 bit but also causes the Timer 2 registers to be reloaded with the 16-bit value held in registers RCAP2L and RCAP2H. The 16-bit value held in these registers is preset by software. * If EXEN2 = 1, Timer 2 operates as described above but with the additional feature that a HIGH-to-LOW transition at external input T2EX will also trigger the 16-bit reload and set the EXF2 bit. 11.2.3 BAUD RATE GENERATOR MODE
Timer 0 and Timer 1 can be programmed independently to operate in four modes: Mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. Mode 1 16-bit time-interval or event counter. Mode 2 8-bit time-interval or event counter with automatic reload upon overflow. Mode 3 Timer 0 establishes TL0 and TH0 as two separate counters. 11.2 Timer T2
The Baud Rate Generator mode is selected when RTCLK = 1. It will be described in conjunction with the serial port (UART); see Section 14.3.2.
Timer T2 is a 16-bit timer/counter that can operate (like Timer 0 and 1) either as a timer or as an event counter. These functions are selected by the state of the C/T2 bit in the T2CON register; see Tables 1 and 2. Three operating modes are available Capture, Auto-reload and Baud Rate Generator, which also are selected via the T2CON register; see Table 3.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
OSC
12
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 capture Timer 2 interrupt RCAP2L RCAP2H EXF2
MLA608
transition detector T2EX PIN control EXEN2
Fig.10 Timer 2 in Capture mode.
handbook, full pagewidth
OSC
12
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 reload Timer 2 interrupt RCAP2L RCAP2H
transition detector T2EX PIN control EXEN2
EXF2
MLA609
Fig.11 Timer 2 in Auto-Reload mode.
1997 Mar 14
19
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
11.3 Timer/Counter 2 Control Register (T2CON) Timer/Counter 2 Control Register (SFR address C8H) 6 EXF2 5 GF2 4 RTCLK 3 EXEN2
P83CL781; P83CL782
Table 1 7 TF2 Table 2 BIT 7 6
2 TR2
1 C/T2
0 CP/RL2
Description of T2CON bits SYMBOL TF2 EXF2 DESCRIPTION Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when RTCLK = 1. Timer 2 external flag. Set when either a capture or reload is caused by a negative transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. EXF2 must be cleared by software. General purpose flag bit. Receive/transmit clock flag. When set, causes the UART serial port to use Timer 2 overflow pulses for its receive and transmit clock in Modes 1 and 3. RTCLK = 0 causes Timer 1 overflows to be used for the receive and transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX, if Timer 2 is not being used to clock the serial port. EXEN2 = 0, causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. TR2 = 1 starts the timer. Timer or counter select for Timer 2. C/T2 = 0 selects the internal timer with a clock frequency of 112 x fosc. C/T2 = 1 selects the external event counter; negative edge triggered. Capture/Reload flag. When set, captures will occur on negative transitions at T2EX, if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When RTCLK = 1, this bit is ignored and the timer is forced to auto-reload on a Timer 2 overflow.
5 4
GF2 RTCLK
3
EXEN2
2 1
TR2 C/T2
0
CP/RL2
Table 3
Timer 2 operating modes; X = don't care CP/RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud Rate Generator Off MODE
RTCLK 0 0 1 X
1997 Mar 14
20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
12 REDUCED POWER MODES There are two software-selectable modes which further reduce power consumption: `Idle' and `Power-down'. 12.1 Idle mode 12.2
P83CL781; P83CL782
Power-down mode
Operation in Power-down mode freezes the oscillator. The internal connections which link both Idle and Power-down signals to the clock generation circuit are shown in Fig.12. Power-down mode is entered by setting the PD bit in the Power Control Register (PCON.1, see Table 5). The instruction that sets PD is the last executed prior to going into the Power-down mode. Once in the Power-down mode, the oscillator is stopped. The contents of the on-chip RAM and the SFRs are preserved. The port pins output the value held by their respective SFRs. ALE and PSEN are held LOW. In the Power-down mode, VDD may be reduced to minimize circuit power consumption. The supply voltage must not be reduced until the Power-down mode is entered, and must be restored before the hardware reset is applied which will free the oscillator. Reset should not be released until the oscillator has restarted and stabilized. 12.3 Wake-up from Power-down mode
Operation in Idle mode permits the interrupt, serial ports and timer blocks to continue to function while the clock to the CPU is halted. Idle mode is entered by setting the IDL bit in the Power Control Register (PCON.0, see Table 5). The instruction that sets IDL is the last instruction executed in the normal operating mode before the Idle mode is activated. Once in the Idle mode, the CPU status is preserved along with the Stack Pointer, Program Counter, Program Status Word and Accumulator. The RAM and all other registers maintain their data during Idle mode. The status of the external pins during Idle mode is shown in Table 4. The following functions remain active during the Idle mode: * Timer 0, Timer 1 and Timer 2 * UART, I2C-bus interface * External interrupt. These functions may generate an interrupt or reset; thus ending the Idle mode. There are two ways to terminate the Idle mode: 1. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware thus terminating the Idle mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the Idle mode. The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When the Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. 2. The second way of terminating the Idle mode is with an external hardware reset, or an internal reset caused by an overflow of Timer T2. Since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. Reset redefines all SFRs but does not affect the on-chip RAM.
When in Power-down mode the controller can be woken-up with either the external interrupts INT2 to INT9, or a reset operation. The wake-up operation has two basic approaches as explained in Section 12.3.1; 12.3.2 and illustrated in Fig.13. 12.3.1 WAKE-UP USING INT2 TO INT9
If any of the interrupts INT2 to INT9 are enabled, the device can be woken-up from the Power-down mode with the external interrupts. To ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 1536 oscillator periods. This is controlled by an on-chip delay counter. 12.3.2 WAKE-UP USING RST
To wake-up the P83CL78x, the RST pin must be kept HIGH for a minimum of 24 periods. The on-chip delay counter is inactive. The user must ensure that the oscillator is stable before any operation is attempted.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
12.4 Status of external pins
P83CL781; P83CL782
If the data is a logic 1, the port pin is held HIGH during the Power-down mode by the strong pull-up transistor `p1'; see Fig.9(a).
The status of the external pins during Idle and Power-down mode is shown in Table 4. If the Power-down mode is activated whilst accessing external Program Memory, the port data that is held in the Special Function Register P2 is restored to Port 2. Table 4
Status of external pins during Idle and Power-down modes MEMORY internal external internal external ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 port data floating port data floating PORT 1 port data port data port data port data PORT 2 port data address port data port data PORT 3 port data port data port data port data
MODE Idle Idle Power-down Power-down 12.5
Power Control Register (PCON)
The reduced power modes are activated by software using this Special Function Register. PCON is not bit addressable. Table 5 7 SMOD Table 6 BIT PCON.7 PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0 Note 1. If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XX00000). Power Control Register (SFR address 87H) 6 - 5 - 4 - 3 GF1 2 GF0 1 PD 0 IDL
Description of PCON bits SYMBOL SMOD - - - GF1 GF0 PD IDL FUNCTION Double Baud rate bit. When set to a logic 1 the baud rate is doubled when the serial port SIO0 is being used in modes 1, 2 or 3. Reserved Reserved Reserved General purpose flag bit General purpose flag bit Power-down bit. Setting this bit activates the Power-down mode; see note 1. Idle mode bit. Setting this bit activates the Idle mode; see note 1.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
XTAL2
XTAL1
OSCILLATOR
interrupts serial ports timer blocks CLOCK GENERATOR CPU
P83CL781 P83CL782
PD IDL
MBB552
Fig.12 Internal clock control in Idle and Power-down modes.
handbook, full pagewidth
power-down
RST pin
external interrupt
oscillator
MGD679
delay counter 1536 periods
24 periods
Fig.13 Wake-up operation.
1997 Mar 14
23
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
13 I2C-BUS SERIAL I/O The serial port supports the twin line I2C-bus, which consists of a serial data line (SDA) and a serial clock line (SCL). These lines also function as the I/O port lines P1.7 and P1.6 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling and operates in 4 modes: * Master transmitter * Master receiver * Slave transmitter * Slave receiver.
P83CL781; P83CL782
These functions are controlled by the Serial Control Register S1CON. S1STA is the Status Register whose contents may also be used as a vector to various service routines. S1DAT is the Data Shift Register and S1ADR is the Slave Address Register. Slave address recognition is performed by on-chip hardware. Figure 14 is the block diagram of the I2C-bus serial I/O.
7 SLAVE ADDRESS S1ADR 7 SDA SHIFT REGISTER GC
0
0
ARBITRATION
SYNC LOGIC
SCL 7
BUS CLOCK GENERATOR 0 CONTROL REGISTER S1CON 7 STATUS REGISTER S1STA
MLB199
0
Fig.14 Block diagram of I2C-bus serial I/O.
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INTERNAL BUS
S1DAT
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
13.1 Serial Control Register (S1CON) Serial Control Register (SFR address D8H) 6 ENS1 5 STA 4 STO 3 SI
P83CL781; P83CL782
Table 7 7 CR2 Table 8 BIT 7 6
2 AA
1 CR1
0 CR0
Description of S1CON bits SYMBOL CR2 ENS1 DESCRIPTION This bit along with bits CR1 (S1CON.1) and CR0 (S1CON.0) determines the serial clock frequency when SIO is in the Master mode. See Table 9. ENABLE serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are in the high impedance state; P1.6 and P1.7 function as open-drain ports. When ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to logic 1. START flag. When this bit is set in Slave mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START condition. STOP flag. With this bit set while in Master mode a STOP condition is generated. When a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag. STO may also be set in Slave mode in order to recover from an error condition. In this case no STOP condition is transmitted to the I2C-bus. However, the SIO hardware behaves as if a STOP condition has been received and releases the SDA and SCL. The SIO then switches to the not addressed slave receiver mode. The STOP flag is cleared by the hardware. SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the following events occur: * A start condition is generated in Master mode * Own slave address has been received during AA = 1 * The general call address has been received while GC (S1ADR.0) = 1 and AA = 1 * A data byte has been received or transmitted in Master mode (even if arbitration is lost) * A data byte has been received or transmitted as selected slave * A Stop or Start condition is received as selected slave receiver or transmitter.
5
STA
4
STO
3
SI
2
AA
Assert Acknowledge. When this bit is set, an acknowledge (low level to SDA) is returned during the acknowledge clock pulse on the SCL line when: * Own slave address is received * General call address is received; GC (S1ADR.0) = 1 * A data byte is received while the device is programmed to be a Master Receiver * A data byte is received while the device is a selected Slave Receiver. When this bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own slave address or general call address is received.
1 0
CR1 CR0
These two bits along with the CR2 (S1CON.7) bit determine the serial clock frequency when SIO is in the Master mode. See Table 9.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
Table 9 CR2 0 0 0 0 1 1 1 1 13.2
P83CL781; P83CL782
Selection of the serial clock frequency SCL in a Master mode of operation CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 fosc DIVISOR 256 224 192 160 960 120 60 not allowed BIT RATE (kHz) AT fosc 3.58 MHz 14.0 16.0 18.6 22.4 3.73 29.8 59.7 - 6 MHz 23.4 26.8 31.3 37.5 6.25 50.0 100.0 - 12 MHz 46.9 53.6 62.5 75.0 12.5 100.0 - -
Serial Status Register (S1STA)
S1STA is a read-only register.The contents of this register may be used as a vector to a service routine. This optimizes the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2C-bus interface are given in Tables 12 to 16. Table 10 Serial Status Register (address D9H) 7 SC4 6 SC3 5 SC2 4 SC1 3 SC0 2 0 1 0 0 0
Table 11 Description of S1STA bits BIT 3 to 7 0 to 2 SYMBOL SC4 to SC0 - 5-bit status code. These three bits are always zero. DESCRIPTION
Table 12 MST/TRX mode S1STA VALUE 08H 10H 18H 20H 28H 30H 38H DESCRIPTION A START condition has been transmitted. A repeated START condition has been transmitted. SLA and W have been transmitted, ACK has been received. SLA and W have been transmitted, ACK received. DATA of S1DAT has been transmitted, ACK received. DATA of S1DAT has been transmitted, ACK received. Arbitration lost in SLA, R/W or DATA.
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26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
Table 13 MST/REC mode S1STA VALUE 08H 10H 38H 40H 48H 50H 58H A START condition has been transmitted. A repeated START condition has been transmitted. Arbitration lost while returning ACK. SLA and R have been transmitted, ACK received. SLA and R have been transmitted, ACK received. DATA has been received, ACK returned. DATA has been received, ACK returned. DESCRIPTION
P83CL781; P83CL782
Table 14 SLV/REC mode S1STA VALUE 60H 68H 70H 78H 80H 88H 90H 98H A0H DESCRIPTION Own SLA and W have been received, ACK returned. Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned. General CALL has been received, ACK returned. Arbitration lost in SLA, R/W as MST. General CALL has been received. Previously addressed with own SLA. DATA byte received, ACK returned. Previously addressed with own SLA. DATA byte received, ACK returned. Previously addressed with general CALL. DATA byte has been received, ACK has been returned. Previously addressed with general CALL. DATA byte has been received, ACK has been returned. A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX.
Table 15 SLV/TRX mode S1STA VALUE A8H B0H B8H C0H C8H DESCRIPTION Own SLA and R have been received, ACK returned. Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned. DATA byte has been transmitted, ACK received. DATA byte has been transmitted, ACK received. Last DATA byte has been transmitted (AA = 0), ACK received.
Table 16 Miscellaneous S1STA VALUE 00H F8H DESCRIPTION Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition. No relevant state information available, SI = 0.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
Table 17 Symbols used in Tables 12 to 16 SYMBOL SLA R W ACK ACK DATA MST SLV TRX REC 13.3 7-bit slave address Read bit Write bit Acknowledgement (acknowledge bit is logic 0) No acknowledgement (acknowledge bit is logic 1) 8-bit data byte to or from I2C-bus Master Slave Transmitter Receiver Data Shift Register (S1DAT) DESCRIPTION
P83CL781; P83CL782
S1DAT contains the serial data to be transmitted or data which has just been received. The MSB (bit 7) is transmitted or received first; i.e. data shifted from right to left. Table 18 Data Shift Register (SFR address DAH) 7 S1DAT.7 13.4 6 S1DAT.6 5 S1DAT.5 4 S1DAT.4 3 S1DAT.3 2 S1DAT.2 1 S1DAT.1 0 S1DAT.0
Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. Table 19 Address Register (SFR address DBH) 7 SLA6 6 SLA5 5 SLA4 4 SLA3 3 SLA2 2 SLA1 1 SLA0 0 GC
Table 20 Description of S1ADR bits BIT 7 to 1 0 SYMBOL SLA6 to SLA0 GC Own slave address. This bit is used to determine whether the general call address is recognized. When GC = 0, the general call address is not recognized; when GC = 1, the general call address is recognized. DESCRIPTION
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
14 STANDARD SERIAL INTERFACE SIO0: UART This serial port is full duplex which means that it can transmit and receive simultaneously. It is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed via the Special Function Register S0BUF. Writing to S0BUF loads the transmit register and reading S0BUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight bits are transmitted/received (LSB first). The baud rate is fixed at 112 x fosc. Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). On receive, the stop bit goes into RB8 in Special Function Register S0CON. The baud rate is variable. Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). On transmit, the 9th data bit (TB8 in S0CON) can be assigned the value of a logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in S0CON, while the stop bit is ignored. The baud rate is programmable to either 132 or 164 x fosc. Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. 14.1
P83CL781; P83CL782
Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th bit goes into RB8. The following bit is the stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated, but only if RB8 = 1. This feature is enabled by setting bit SM2 in S0CON. One use of this feature, in multiprocessor systems, is as follows. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is HIGH in an address byte and LOW in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be sent. The slaves that were not being addressed leave their SM2 bits set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
14.2 Serial Port Control and Status Register (S0CON)
P83CL781; P83CL782
The Serial Port Control and Status Register is the Special Function Register S0CON. The register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Table 21 Serial Port Control Register (address 98H) 7 SMO 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Table 22 Description of S0CON bits BIT 7 6 5 SYMBOL SM0 SM1 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be a logic 0. Enables serial reception and is set by software to enable reception, and cleared by software to disable reception. Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as desired. In Modes 2 and 3, is the 9th data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop bit that was received. In Mode 0, RB8 is not used. The transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. Must be cleared by software. The receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (except see SM2). Must be cleared by software. DESCRIPTION These bits are used to select the serial port mode; see Table 23.
4 3 2 1
REN TB8 RB8 TI
0
RI
Table 23 Selection of the serial port modes SMO 0 0 1 1 SM1 0 1 0 1 MODE Mode 0 Mode 1 Mode 2 Mode 3 DESCRIPTION Shift register 8-bit UART 9-bit UART 9-bit UART
1 32
BAUD RATE
1 12
x fosc
variable or 164 x fosc variable
1997 Mar 14
30
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
14.3 Baud rates
P83CL781; P83CL782
The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either `timer' or `counter' operation in any of its 3 running modes. In most typical applications, it is configured for `timer' operation, in the Auto-reload mode (high nibble of TMOD = 0010B). In this case the baud rate is given by the formula:
SMOD f osc 2 Baud Rate = ---------------- x ------------------------------------------------------32 { 12 x ( 256 - TH1 ) }
The baud rate in Mode 0 is fixed and may be calculated as: f osc Baud Rate = -------12 The baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON and may be calculated as: 2 Baud Rate = ---------------- x f osc 64 * If SMOD = 0 (value on reset), the baud rate is * If SMOD = 1, the baud rate is 132 x fosc The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. 14.3.1 USING TIMER 1 TO GENERATE BAUD RATES
1 x f 64 osc SMOD
By configuring Timer 1 to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload, very low baud rates can be achieved. Table 24 lists commonly used baud rates and how they can be obtained from Timer 1.
When Timer 1 is used as the Baud Rate Generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of the SMOD bit as follows: 2 Baud Rate = ---------------- x Timer 1 Overflow Rate. 32 Table 24 Commonly used baud rates generated by Timer 1 BAUD RATE (kb/s) 1000.0(1) 375.0(3) 62.5(4) 19.2 9.6 4.8 2.4 1.2 137.5 110.0 110.0 Notes 1. Maximum in Mode 0. 2. X = don't care. 3. Maximum in Mode 2. 4. Maximum in Modes 1 and 3. fosc (MHz) 12.000 12.000 12.000 11.059 11.059 11.059 11.059 11.059 11.986 6.000 12.000 SMOD X(2) 1 1 1 0 0 0 0 0 0 0 C/T X X 0 0 0 0 0 0 0 0 0 TIMER 1 MODE X X Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 2 Mode 1 RELOAD VALUE X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH
SMOD
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31
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
14.3.2 USING TIMER 2 TO GENERATE BAUD RATES
P83CL781; P83CL782
Where (RCAP2H; RCAP2L) is the content of registers RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Baud Rate Generator mode for Timer 2 is shown in Fig.15. This figure is only valid if RTCLK = 1. At roll-over TH2 does not set the TF2 bit in T2CON and therefore, will not generate an interrupt. Consequently, the Timer 2 interrupt does not need to be disabled when in the Baud Rate Generator mode. If EXEN2 is set, a HIGH-to-LOW transition on T2EX will set the EXF2 bit, also in T2CON, but will not cause a reload from (RCAP2H; RCAP2L) to (TH2, TL2). Therefore, in this mode T2EX may be used as an additional external interrupt. When Timer 2 is operating as a timer (TR2 = 1), in the Baud Rate Generator mode, registers TH2 and TL2 should not be accessed (read or write). Under these conditions the timer is being incremented every state time and therefore the results of a read or write may not be accurate. The registers RCAP2H and RCAP2L however, may be read but not written to. A write might overlap a reload and cause write and/or reload errors. If a write operation is required, Timer 2 or RCAP2H/RCAP2L should first be turned off by clearing the TR2 bit.
Timer 2 is selected as a Baud Rate Generator by setting the RTCLK bit in T2CON. The Baud Rate Generator mode is similar to the Auto-reload mode, in that a roll-over in TH2 causes Timer 2 registers to be reloaded with the 16-bit value held in the registers RCAP2H and RCAP2L, which are preset by software. Baud rates in Modes 1 and 3 are determined by Timer 2's overflow rate as specified below. Timer 2 Overflow Rate Baud Rate = ----------------------------------------------------------16 The Timer 2 can be configured for either `timer' or `counter' operation. In the most typical applications, it is configured for `timer' operation (C/T2 = 0). `Timer' operation is slightly different for Timer 2 when it is being used as a Baud Rate Generator. Normally, as a timer it would increment every machine cycle at a frequency of 112 x fosc. However, as a Baud Rate Generator it increments every state time at a frequency of 12 x fosc. In this case the baud rate in Modes 1 and 3 is determined as: f osc Baud Rate = ---------------------------------------------------------------------------------------------------32 x { 65536 - ( RCAP2H; RCAP2L ) }
handbook, full pagewidth
TIMER 1 overflow 2 (note: divided by 2 not by 12) 0 1 SMOD TL2 (8 BITS) T2 PIN C/T2 = 1 control TR2 RELOAD 16 UART receive/ transmit clock transition detector T2EX PIN control EXEN2 RCAP2L RCAP2H CLK TH2 (8 BITS) 1 0 RTCLK
OSC
2
C/T2 = 0
EXF2
TIMER 2 interrupt (additional external interrupt)
MGD622
Fig.15 Timer 2 in Baud Rate Generator mode.
1997 Mar 14
32
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
INTERNAL BUS
write to SBUF RXD P3.0 ALT output function SHIFT
DS CL
Q
S0 BUFFER
ZERO DETECTOR
START S6 TX CLOCK
TX CONTROL
T1
SHIFT SEND
serial port interrupt SHIFT CLOCK R1
TXD P3.1 ALT output function
RX CLOCK REN RI START
RECEIVE
RX CONTROL
SHIFT 1 1 11111 0
INPUT SHIFT REGISTER SHIFT LOAD SBUF
RXD P3.0 ALT input function
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC752
Fig.16 Serial port Mode 0.
1997 Mar 14
33
P83CL781; P83CL782
Product specification
Fig.17 Serial port Mode 0 timing.
handbook, full pagewidth
1997 Mar 14
D1 D2 D3 D4 D5 D6 D7 T R A N S M I T S6P1
Philips Semiconductors
...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6
ALE
WRITE TO SBUF
SEND
S6P2
SHIFT
RXD (DATA OUT)
D0
TSC (SHIFT CLOCK)
S3P1
Low voltage 8-bit microcontrollers with UART and I2C-bus
WRITE TO SCON (CLEAR R1)
34
D0 D1 D2 D3 D4 D5 D6 D7
MLA567
RI
RECEIVE
R E C E I V E
SHIFT RXD (DATA IN)
S5P2
TXD (SHIFT CLOCK)
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
INTERNAL BUS TB8
Timer 1 overflow
Timer 2 overflow
write to SBUF
2 0 SMOD RTCLK 1 0 1
DS Q CL
S0 BUFFER
TXD
ZERO DETECTOR
SHIFT
START 16 TX CLOCK
TX CONTROL
T1
SHIFT DATA SEND
serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC755
Fig.18 Serial port Mode 1.
1997 Mar 14
35
P83CL781; P83CL782
Product specification
Fig.19 Serial port Mode 1 timing.
handbook, full pagewidth
1997 Mar 14
D0 D1 D6 D2 D3 D7 D4 D5 STOP BIT T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
SEND
DATA
S1P1
SHIFT
TXD
START BIT
TI
Low voltage 8-bit microcontrollers with UART and I2C-bus
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT
36
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
RI
MLA569
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF
phase 2 clock (fosc / 2)
DS CL
Q
S0 BUFFER
TXD
2 0 CSMOD at PCON.7 1 SHIFT ZERO DETECTOR
STOP BIT START 16 TX CLOCK
TX CONTROL
T1
SHIFT DATA SEND
serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC754
Fig.20 Serial port Mode 2.
1997 Mar 14
37
P83CL781; P83CL782
Product specification
Fig.21 Serial port Mode 2 timing.
handbook, full pagewidth
1997 Mar 14
D0 STOP BIT D1 D2 D3 D7 TB8 D4 D5 D6 T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
SEND
DATA
S1P1
SHIFT
TXD
START BIT
TI
STOP BIT GEN
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT
Low voltage 8-bit microcontrollers with UART and I2C-bus
38
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
MLA571
RI
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF Timer 1 overflow Timer 2 overflow
DS CL
Q
S0 BUFFER
TXD
2 0 SMOD RTCLK SHIFT DATA SEND T1 serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT 1 0 1 ZERO DETECTOR SHIFT
START 16 TX CLOCK
TX CONTROL
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC753
Fig.22 Serial port Mode 3.
1997 Mar 14
39
P83CL781; P83CL782
Product specification
Fig.23 Serial port Mode 3 timing.
handbook, full pagewidth
1997 Mar 14
D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT T R A N S M I T /16 RESET
Philips Semiconductors
TX CLOCK
WRITE TO SBUF
DATA
SEND
S1P1
SHIFT
TXD
START BIT
TI
Low voltage 8-bit microcontrollers with UART and I2C-bus
RX CLOCK START BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT
40
RXD
R E C E I V E
BIT DETECTOR SAMPLE TIME
SHIFT
RI
MLA573
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
15 INTERRUPT SYSTEM External events and the real-time-driven on-chip peripherals require service by the CPU at unpredictable times. To tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. The system is shown in Fig.24. The P83CL78x acknowledges interrupt requests from fifteen sources as follows: * INT0 to INT9 * Timer 0, Timer 1 and Timer 2 * I2C-bus serial I/O * UART. Each interrupt vectors to a separate location in Program Memory for its service routine. Each source can be individually enabled or disabled by its corresponding bit in the Interrupt Enable Registers (IEN0 and IEN1). The priority level is selected via the Interrupt Priority Registers (IP0 and IP1). All enabled sources can be globally disabled or enabled. 15.1 External interrupts INT2 to INT9 15.2
P83CL781; P83CL782
Interrupt priority
Each interrupt source can be set to either a high priority or to a low priority. If a low priority interrupt is received simultaneously with a high priority interrupt, the high priority interrupt will be dealt with first. If interrupts of the same priority are requested simultaneously, the processor will branch to the interrupt polled first, according to the sequence shown in Table 25 and in Fig.24. The `vector address' is the ROM location where the appropriate interrupt service routine starts. Table 25 Interrupt vector polling sequence SYMBOL X0 (first) S1 X5 T0 T2 X6 X1 X2 X7 T1 X3 X8 SO X4 X9 (last) VECTOR ADDRESS (HEX) 0003 002B 0053 000B 0033 005B 0013 003B 0063 001B 0043 006B 0023 004B 0073 SOURCE External 0 I2C port External 5 Timer 0 Timer 2 External 6 External 1 External 2 External 7 Timer 1 External 3 External 8 UART External 4 External 9
Port 1 lines serve an alternative purpose as eight additional interrupts INT2 to INT9. When enabled, each of these lines may wake-up the device from the Power-down mode. Using the Interrupt Polarity Register (IX1), each pin may be initialized to be either active HIGH or active LOW. IRQ1 is the Interrupt Request Flag Register. If the interrupt is enabled, each flag will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disabled. Port 1 interrupts are level-sensitive. A Port 1 interrupt will be recognized when a level (HIGH or LOW depending on the Interrupt Polarity Register) on P1.n is held active for at least one machine cycle. The interrupt request is not serviced until the next machine cycle. Figure 25 shows the external interrupt system.
A low priority interrupt routine can only be interrupted by a high priority interrupt. A high priority interrupt routine cannot be interrupted.
1997 Mar 14
41
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
INTERRUPT SOURCES X0
IEN0/1 REGISTERS
IP0/1
PRIORITY HIGH LOW
S1
X5
T0
T2
X6 INTERRUPT POLLING SEQUENCE GLOBAL ENABLE
MLA611
X1
X2
X7
T1
X3
X8
S0
X4
X9
Fig.24 Interrupt system.
1997 Mar 14
42
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, full pagewidth
IX1
IEN1
IRQ1 X9
P1.7
P1.6
X8
P1.5
X7
P1.4
X6
P1.3
X5
P1.2
X4
P1.1
X3
P1.0
X2
MLA575
WAKE-UP
Fig.25 External interrupt configuration.
15.3
Interrupt registers
The registers used in the interrupt system are listed in Table 26. Tables 27 to 38 describe the contents of these registers. Table 26 Special Function Registers related to the interrupt system ADDRESS A8H E8H B8H F8H E9H C0H REGISTER IEN0 IEN1 IP0 IP1 IX1 IRQ1 Interrupt Enable Register Interrupt Enable Register (INT2 to INT9) Interrupt Priority Register Interrupt Priority Register (INT2 to INT9) Interrupt Polarity Register Interrupt Request Flag Register DESCRIPTION
1997 Mar 14
43
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
15.3.1 INTERRUPT ENABLE REGISTER (IEN0)
P83CL781; P83CL782
Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 27 Interrupt Enable Register (SFR address A8H) 7 EA 6 ET2 5 ES1 4 ES0 3 ET1 2 EX1 1 ET0 0 EX0
Table 28 Description of IEN0 bits BIT 7 6 5 4 3 2 1 0 15.3.2 SYMBOL EA ET2 ES1 ES0 ET1 EX1 ET0 EX0 DESCRIPTION General enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any individually enabled interrupt will be accepted. enable T2 interrupt enable I2C interrupt enable UART SIO interrupt enable Timer 1 interrupt (T1) enable external interrupt 1 enable Timer 0 interrupt (T0) enable external interrupt 0
INTERRUPT ENABLE REGISTER (IEN1)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 29 Interrupt Enable Register (SFR address E8H) 7 EX9 6 EX8 5 EX7 4 EX6 3 EX5 2 EX4 1 EX3 0 EX2
Table 30 Description of IEN1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL EX9 EX8 EX7 EX7 EX5 EX4 EX3 EX2 enable external interrupt 9 enable external interrupt 8 enable external interrupt 7 enable external interrupt 6 enable external interrupt 5 enable external interrupt 4 enable external interrupt 3 enable external interrupt 2 DESCRIPTION
1997 Mar 14
44
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
15.3.3 INTERRUPT PRIORITY REGISTER (IP0)
P83CL781; P83CL782
Bit values: 0 = low priority; 1 = high priority. Table 31 Interrupt Priority Register (SFR address B8H) 7 - 6 PT2 5 PS1 4 PS0 3 PT1 2 PX1 1 PT0 0 PX0
Table 32 Description of IP0 bits BIT 7 6 5 4 3 2 1 0 15.3.4 SYMBOL - PT2 PS1 PS0 PT1 PX1 PT0 PX0 reserved Timer 2 interrupt priority level I2C interrupt priority level UART SIO interrupt priority level Timer 1 interrupt priority level external interrupt 1 priority level Timer 0 interrupt priority level external interrupt 0 priority level DESCRIPTION
INTERRUPT PRIORITY REGISTER (IP1)
Bit values: 0 = low priority; 1 = high priority. Table 33 Interrupt Priority Register (SFR address F8H) 7 PX9 6 PX8 5 PX7 4 PX6 3 PX5 2 PX4 1 PX3 0 PX2
Table 34 Description of IP1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 external interrupt 9 priority level external interrupt 8 priority level external interrupt 7 priority level external interrupt 6 priority level external interrupt 5 priority level external interrupt 4 priority level external interrupt 3 priority level external interrupt 2 priority level DESCRIPTION
1997 Mar 14
45
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
15.3.5 INTERRUPT POLARITY REGISTER (IX1)
P83CL781; P83CL782
Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external interrupt to an active HIGH or active LOW respectively. Table 35 Interrupt Polarity Register (SFR address E9H) 7 IL9 6 IL8 5 IL7 4 IL6 3 IL5 2 IL4 1 IL3 0 IL2
Table 36 Description of IX1 bits BIT 7 6 5 4 3 2 1 0 15.3.6 SYMBOL IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 external interrupt 9 polarity level external interrupt 8 polarity level external interrupt 7 polarity level external interrupt 6 polarity level external interrupt 5 polarity level external interrupt 4 polarity level external interrupt 3 polarity level external interrupt 2 polarity level DESCRIPTION
INTERRUPT REQUEST FLAG REGISTER (IRQ1)
Table 37 Interrupt Request Flag Register (SFR address C0H) 7 IQ9 6 IQ8 5 IQ7 4 IQ6 3 IQ5 2 IQ4 1 IQ3 0 IQ2
Table 38 Description of IRQ1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 external interrupt 9 request flag external interrupt 8 request flag external interrupt 7 request flag external interrupt 6 request flag external interrupt 5 request flag external interrupt 4 request flag external interrupt 3 request flag external interrupt 2 request flag DESCRIPTION
1997 Mar 14
46
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
16 OSCILLATOR CIRCUITRY The on-chip oscillator circuitry of the P8xCL580 is a single-stage inverting amplifier biased by an internal feedback resistor. The oscillator circuit is shown in Fig.26. For operation as a standard quartz oscillator, no external components are needed, except for the 32 kHz option. When using external capacitors, ceramic resonators, coils and RC networks to drive the oscillator, five different configurations are supported (see Table 39 and Fig.26). In the Power-down mode the oscillator is stopped and XTAL1 is pulled HIGH. The oscillator inverter is switched off to ensure no current will flow regardless of the voltage at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of Fig.26. Table 39 Oscillator options OPTION Oscillator 1 Oscillator 2 Oscillator 3 Oscillator 4 RC oscillator APPLICATION
P83CL781; P83CL782
To drive the device with an external clock source, apply the external clock signal to XTAL1, and leave XTAL2 to float, as shown in Fig.26(f). There are no requirements on the duty cycle of the external clock, since the input to the internal clocking circuitry is buffered by a flip-flop. Various oscillator options are provided for optimum on-chip oscillator performance; these are specified in Table 40 and shown in Fig.26. The required option should be stated when ordering.
For 32 kHz clock applications with external trimmer for frequency adjustment. A 4.7 M bias resistor is needed for use in parallel with the crystal; see Fig.26(c). Low-power, low-frequency operations using LC components; see Fig.26(e). Medium frequency range applications. High frequency range applications. RC oscillator configuration; see Figs 26(g) and 28.
handbook, full pagewidth
STANDARD QUARTZ OSCILLATOR XTAL1 XTAL2
QUARTZ OSCILLATOR WITH EXTERNAL CAPACITORS
32 kHz OSCILLATOR XTAL1 XTAL2
XTAL1
XTAL2
(a)
(b)
(c)
CERAMIC RESONATOR XTAL1 XTAL2
LC - OSCILLATOR XTAL1 XTAL2
EXTERNAL CLOCK XTAL1 XTAL2 n.c.
RC - OSCILLATOR XTAL1 n.c. VDD XTAL2
(d)
(e)
(f)
(g)
MLA577
Fig.26 Oscillator configurations.
1997 Mar 14
47
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
VDD
P83CL781 P83CL782
VDD PD
to internal timing circuits
VDD
C1 i
R bias
C2 i
XTAL1
XTAL2
MLA613
Fig.27 Standard oscillator.
MLA579
handbook, halfpage
600
f osc (kHz)
400
200
0 0 2 4 RC (s) 6
RC oscillator frequency is externally adjustable; 100 kHz fosc 500 kHz.
Fig.28 RC oscillator; frequency as a function of RC.
1997 Mar 14
48
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
Table 40 Oscillator type selection guide RESONATOR Quartz FREQUENCY (MHz) 0.032 1.0 3.58 4.0 6.0 10.0 12.0 16.0 PXE 0.455 1.0 3.58 4.0 6.0 10.0 12.0 LC Oscillator 3 Oscillator 4 Oscillator 2 Oscillator 2 Oscillator 4 Oscillator 3 Oscillator 2 OPTION (see Table 39) Oscillator 1 C1 EXT. (pF) MIN. 0 0 0 0 0 0 0 0 40 15 0 0 0 0 10 20 MAX. 0 30 15 20 10 15 10 15 50 50 40 40 20 15 40 90
P83CL781; P83CL782
C2 EXT. (pF) MIN. 5 0 0 0 0 0 0 0 40 15 0 0 0 0 10 20 MAX. 15 30 15 20 10 15 10 15 50 50 40 40 20 15 40 90
RESONATOR MAX. SERIES RESISTANCE 15 k; note 1 600 100 75 60 60 40 20 10 100 10 10 5 6 6 10 H = 1 100 H = 5 1 mH = 75
Note 1. 32 kHz quartz crystals with a series resistance >15 k will reduce the guaranteed supply voltage range to 2.5 to 3.5 V.
1997 Mar 14
49
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
Rf
handbook, full pagewidth
XTAL1 C1 i V1 gm R2 C2 i
XTAL2
MLA578
Fig.29 Oscillator equivalent circuit diagram.
Table 41 Oscillator equivalent circuit parameters The equivalent circuit data of the internal oscillator compares with that of matched crystals. SYMBOL gm PARAMETER transconductance OPTION Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 C1i input capacitance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 C2i output capacitance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 R2 output resistance Oscillator 1; 32 kHz Oscillator 2 Oscillator 3 Oscillator 4 CONDITION Tamb = +25 C; VDD = 4.5 V - 200 400 1000 - - - - - - - - - - - - MIN. TYP. 15 600 1500 4000 3.0 8.0 8.0 8.0 23 8.0 8.0 8.0 3800 65 18 5.0 MAX. - 1000 4000 10000 - - - - - - - - - - - - UNIT S S S S pF pF pF pF pF pF pF pF k k k k
1997 Mar 14
50
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
17 RESET To initialize the P83CL78x a reset is performed by either of two methods: * Applying an external signal to the RST pin * Via Power-on reset circuitry. The reset state of the port pins is mask-programmable and can be defined by the user. The standard reset value for Ports 0 to 3 is FFH. A reset leaves the internal registers as shown in Chapter 18. 17.1 External reset using the RST pin 17.2
P83CL781; P83CL782
Power-on reset
The device contains on-chip circuitry which switches the port pins to the customer defined logic level as soon as VDD exceeds 1.3 V; if the mask option `ON' has been chosen. As soon as the minimum supply voltage is reached, the oscillator will start up. However, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the CPU for a further 1536 oscillator periods. A hysteresis of approximately 50 mV at a typical power-on switching level of 1.3 V will ensure correct operation. See Fig.32. The on-chip Power-on reset circuitry can also be switched off via the mask option `OFF'. This option reduces the Power-down current to typically 800 nA and can be chosen if external reset circuitry is used. For applications not requiring the internal reset, option `OFF' should be chosen. An automatic reset can be obtained by connecting the RST pin to VDD via a 10 F capacitor. At power-on, the voltage on the RST pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor charges through the internal resistor (RRST) to ground. The larger the capacitor, the more slowly VRST decreases. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles. The Power-on reset circuitry is shown in Fig.31.
The reset input for the P83CL78x is RST. A Schmitt trigger is used at the input for noise rejection. The output of the Schmitt trigger is sampled by the reset circuitry every machine cycle. A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by executing an internal reset. Port pins adopt their reset state immediately after the RST goes HIGH. During reset, ALE and PSEN are held HIGH. The external reset is asynchronous to the internal clock. The RST pin is sampled during state 5, phase 2 of every machine cycle. After a HIGH is detected at the RST pin, an internal reset is repeated until RST goes LOW. The internal RAM is not affected by reset. When VDD is turned on, the RAM contents are indeterminate.
VDD
handbook, halfpage
SCHMITT TRIGGER RESET CIRCUITRY
MLA580
10 F
V DD
P83CL781 P83CL782
RST
RST
R RST
MLA612
Fig.30 Reset configuration.
Fig.31 Power-on reset circuitry.
1997 Mar 14
51
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
switching level POR
handbook, full pagewidth SUPPLY
VOLTAGE
hysteresis
POWER-ON-RESET (INTERNAL)
OSCILLATOR
CPU RUNNING
MLA581
Start-up time
1536 oscillator periods delay
Fig.32 Power-on reset switching level.
1997 Mar 14
52
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
18 SPECIAL FUNCTION REGISTERS OVERVIEW The P83CL78x has 34 SFRs available to the user. ADDRESS (HEX) F8 F0 E9 E8 E0 DB DA D9 D8 D0 CD CC CB CA C8 C0 B8 B0 A8 A0 99 98 90 8D 8C 8B 8A 89 88 87 83 82 81 80 Notes 1. Bit addressable register. 2. Port reset state determined by the customer. B(1) IX1 IEN1(1) ACC(1) S1ADR S1DAT S1STA S1CON(1) PSW(1) TH2 TL2 RCAP2H RCAP2L T2CON(1) IRQ1(1) IP0(1) P3(1) IEN0(1) P2(1) S0BUF S0CON(1) P1(1) TH1 TH0 TL1 TL0 TMOD TCON(1) PCON DPH DPL SP P0(1) NAME IP1(1) RESET VALUE (B) 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 X0000000 XXXXXXXX(2) 00000000 XXXXXXXX(2) XXXXXXXX 00000000 XXXXXXXX(2) 00000000 00000000 00000000 00000000 00000000 00000000 0XX00000 00000000 00000000 00000111 XXXXXXXX(2) B Register Interrupt Polarity Register Interrupt Enable Register 1 Accumulator I2C-bus Slave Address Register I2C-bus Data Shift Register I2C-bus Serial Status Register I2C-bus Serial Control Register Program Status Word Timer 2 High byte Timer 2 Low byte
P83CL781; P83CL782
FUNCTION Interrupt Priority Register (INT2 to INT9)
Timer 2 Reload/Capture Register High byte Timer 2 Reload/Capture Register Low byte Timer/Counter 2 Control Register Interrupt Request Flag Register Interrupt Priority Register 0 Digital I/O Port Register 3 Interrupt Enable Register Digital I/O Port Register 2 Serial Data Buffer Register 0 Serial Port Control Register 0 Digital I/O Port Register 1 Timer 1 High byte Timer 0 High byte Timer 1 Low byte Timer 0 Low byte Timer 0 and 1 Mode Control Register Timer 0 and 1 Control/External Interrupt Control Register Power Control Register Data Pointer High byte Data Pointer Low byte Stack Pointer Digital I/O Port Register 0
1997 Mar 14
53
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
19 INSTRUCTION SET
P83CL781; P83CL782
The P83CL78x uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz oscillator, 64 instructions execute in 1 s and 45 instructions execute in 2 s. Multiply and divide instructions execute in 4 s. For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 46. Table 42 Instruction set description: Arithmetic operations MNEMONIC Arithmetic operations ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A Rr direct @Ri A Rr direct @Ri DPTR AB AB A Add register to A Add direct byte to A Add indirect RAM to A Add immediate data to A Add register to A with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 2* 25 26, 27 24 3* 35 36, 37 34 9* 95 96, 97 94 04 0* 05 06, 07 14 1* 15 16, 17 A3 A4 84 D4 DESCRIPTION BYTES CYCLES OPCODE (HEX)
1997 Mar 14
54
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
Table 43 Instruction set description: Logic operations MNEMONIC Logic operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A A A A A A A AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate data to A Exclusive-OR A to direct byte Exclusive-OR immediate data to direct byte Clear A Complement A Rotate A left Rotate A left through the carry flag Rotate A right Rotate A right through the carry flag Swap nibbles within A DESCRIPTION
P83CL781; P83CL782
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1
1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
5* 55 56, 57 54 52 53 4* 45 46, 47 44 42 43 6* 65 66, 67 64 62 63 E4 F4 23 33 03 13 C4
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55
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
Table 44 Instruction set description: Data transfer MNEMONIC Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD Note 1. MOV A,ACC is not permitted. A,Rr A,@Ri A,#data Rr,A Rr,direct Rr,#data direct,A direct,Rr direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rr A,direct A,@Ri A,@Ri Move register to A Move indirect RAM to A Move immediate data to A Move A to register Move direct byte to register Move immediate data to register Move A to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Move code byte relative to DPTR to A Move code byte relative to PC to A Move external RAM (8-bit address) to A Move external RAM (16-bit address) to A Move A to external RAM (8-bit address) Move A to external RAM (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange register with A Exchange direct byte with A Exchange indirect RAM with A Exchange LOW-order digit indirect RAM with A DESCRIPTION
P83CL781; P83CL782
BYTES
CYCLES
OPCODE (HEX)
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1
E* E5 E6, E7 74 F* A* 7* F5 8* 85 86, 87 75 F6, F7 A6, A7 76, 77 90 93 83 E2, E3 E0 F2, F3 F0 C0 D0 C* C5 C6, C7 D6, D7
A,direct (note 1) Move direct byte to A
DPTR,#data 16 Load data pointer with a 16-bit constant
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56
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
Table 45 Instruction set description: Boolean variable manipulation, Program and machine control MNEMONIC Boolean variable manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag Move direct bit to carry flag Move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 *1 12 22 32 1 02 80 73 60 70 40 50 20 30 10 B5 B4 B* B6, B7 D* D5 00 DESCRIPTION BYTES CYCLES OPCODE (HEX)
Program and machine control ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel @A+DPTR rel rel rel rel bit,rel bit,rel bit,rel A,direct,rel A,#data,rel Rr,#data,rel Rr,rel direct,rel addr11 addr16 Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if A is zero Jump if A is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to register and jump if not equal Decrement register and jump if not zero Decrement direct and jump if not zero No operation 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
@Ri,#data,rel Compare immediate to indirect and jump if not equal
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
Table 46 Description of the mnemonics in the Instruction set MNEMONIC Data addressing modes Rr direct @Ri #data #data 16 bit addr16 addr11 rel Working register R0-R7. DESCRIPTION
P83CL781; P83CL782
128 internal RAM locations and any special function register (SFR). Indirect internal RAM location addressed by register R0 or R1 of the actual register bank. 8-bit constant included in instruction. 16-bit constant included as bytes 2 and 3 of instruction. Direct addressed bit in internal RAM or SFR. 16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the 64 kbytes Program Memory address space. 111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes page of Program Memory as the first byte of the following instruction. Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference * * 8, 9, A, B, C, D, E, F. 1, 3, 5, 7, 9, B, D, F. 0, 2, 4, 6, 8, A, C, E.
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Table 47 Instruction map Second hexadecimal character of opcode 6 INC @Ri 0 DEC @Ri 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPL A MOV direct,A 0 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 1 0 7 7 8 F
First hexadecimal character of opcode
1997 Mar 14 3 RR A RRC A RL A RLC A 4 INC A DEC A ADD A,#data ADDC A,#data 5 INC direct DEC direct ADD A,direct ADDC A,direct
0
0
NOP
Philips Semiconductors
1
2 LJMP addr16 LCALL addr16
2
RET
3
JBC bit,rel JB bit,rel JNB bit,rel
1 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11
RETI
4
5
6
Low voltage 8-bit microcontrollers with UART and I2C-bus
7
59 CJNE A,direct,rel XCH A,direct DJNZ direct,rel MOV A,direct (1)
8
9
ORL A,direct ANL A,direct XRL A,direct MOV direct,#data MOV direct,direct SUBB A,direct
A
B
C
D
E
JC rel JNC rel JZ rel JNZ rel SJMP rel MOV DTPR,#data16 ORL C,/bit ANL C,/bit PUSH direct POP direct MOVX A,@DTPR
AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11
ORL A,#data ANL A,#data XRL A,#data MOV A,#data DIV AB SUBB A,#data MUL AB CJNE A,#data,rel SWAP A DA A CLR A
F
MOVX @DTPR,A
ACALL addr11
ORL ORL direct,A direct,#data ANL ANL direct,A direct,#data XRL XRL direct,A direct,#data ORL JMP C,bit @A+DPTR ANL MOVC C,bit A,@A+PC MOV MOVC bit,C A,@A+DPTR MOV INC bit,C DPTR CPL CPL bit C CLR CLR bit C SETB SETB bit C MOVX A,@Ri 0 1 MOVX @Ri,A 0 1
0 1 ADD A,@Ri 0 1 ADDC A,@Ri 0 1 ORL A,@Ri 0 1 ANL A,@Ri 0 1 XRL A,@Ri 0 1 MOV @Ri,#data 0 1 MOV direct,@Ri 0 1 SUBB A,@Ri 0 1 MOV @Ri,direct 0 1 CJNE @Ri,#data,rel 0 1 XCH A,@Ri 0 1 XCHD A,@Ri 0 1 MOV A,@Ri 0 1 MOV @Ri,A 0 1
9ABCDE INC Rr 123456 DEC Rr 123456 ADD A,Rr 123456 ADDC A,Rr 123456 ORL A,Rr 123456 ANL A,Rr 123456 XRL A,Rr 123456 MOV Rr,#data 123456 MOV direct,Rr 123456 SUB A,Rr 123456 MOV Rr,direct 123456 CJNE Rr,#data,rel 123456 XCH A,Rr 123456 DJNZ Rr,rel 123456 MOV A,Rr 123456 MOV Rr,A 123456
P83CL781; P83CL782
Note
Product specification
1. MOV A, ACC is not a valid instruction.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
20 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD VI II IO Ptot Tstg Tamb Tj supply voltage input voltage on any pin with respect to ground (VSS) DC current on any input DC current on any output total power dissipation storage temperature operating ambient temperature - P83CL781 operating ambient temperature - P83CL782 operating junction temperature PARAMETER
P83CL781; P83CL782
MIN. -0.5 -0.5 -5.0 -5.0 - -65 -40 -25 -
MAX. +6.5 +5.0 +5.0 300 +150 +85 +55 +125 V VDD + 0.5 V
UNIT
mA mA mW C C C C
21 DC CHARACTERISTICS The DC characteristics apply to both the P83CL781 and the P83CL782 unless otherwise stated. VDD = 1.8 to 6 V; VSS = 0 V; Tamb = -40 to +85 C for the P83CL781 and -25 to +55 C for the P83CL782; all voltages with respect to VSS unless otherwise specified. See notes 1, 2 and 3. SYMBOL Supply VDD VDD IDD supply voltage RAM retention voltage in Power-down mode supply current operating; P83CL781 supply current operating; P83CL782 IDD(idle) supply current Idle mode; P83CL781 supply current Idle mode; P83CL782 IDD(pd) supply current Power-down mode VDD = 5 V; fCLK = 12 MHz; note 4 VDD = 3 V; fCLK = 3.58 MHz; note 4 VDD = 3.1 V; fCLK = 12 MHz; note 4 VDD = 3 V; fCLK = 3.58 MHz; note 4 VDD = 5 V; fCLK = 12 MHz; note 5 VDD = 3 V; fCLK = 3.58 MHz; note 5 VDD = 5 V; fCLK = 12 MHz; note 5 VDD = 3 V; fCLK = 3.58 MHz; note 5 VDD = 1.8 V; Tamb = 25 C; note 6 1.8 1.0 - - - - - - - - - - - 17 2.4 8.4 2.4 5.1 0.75 2.7 0.75 - 6.0 6.0 25 5 12 5 12 3 5 3 10 V V mA mA mA A mA mA mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
SYMBOL Inputs VIL VIH IIL IIL(T) ILI Outputs IOL IOL1 IOH RRST Notes
PARAMETER
CONDITIONS
MIN.
TYP. - - - - - - - - - - - -
MAX.
UNIT
LOW level input voltage HIGH level input voltage LOW level input current LOW level input current (HIGH-to-LOW transition) input leakage current
note 7 note 7 VDD = 5 V; VIN = 0.4 V; note 7 VDD = 2.5 V; VIN = 0.4 V; note 7 VDD = 5 V; VIN = 0.5VDD; note 7 VDD = 2.5 V; VIN = 0.5VDD; note 7 VSS < VI < VDD; note 7 VDD = 5 V; VOL = 0.4 V VDD = 2.5 V; VOL = 0.4 V VDD = 5 V; VOL = 0.4 V VDD = 5 V; VOH = VDD - 0.4 V VDD = 2.5 V; VOH = VDD - 0.4 V
VSS - - - - - 1.6 0.7 3.0 -1.6 -0.7 10
0.3VDD V VDD -100 -50 -1.0 -500 10 - - - - - 200 V A A mA A A mA mA mA mA mA k
0.7VDD -
LOW level output current; except SDA and SCL LOW level output current; SDA and SCL HIGH level output current (push-pull options only) RST pull-down resistor
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port 1 and Port 3 pins when these make a HIGH-to-LOW transition during bus operations. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH-to-LOW transitions during bus operations. In the most adverse conditions (capacitive loading >100 pF), the noise pulse on the ALE line may exceed 0.8 V. In such events it may be required to qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger strobe input. 2. Capacitive loading on Ports 0 and 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9% of VDD specification when the address bits are stabilizing. 3. Circuits with Power-on reset option `OFF' are tested at VDDmin = 1.8 V; with the `ON' option (typically 1.3 V) they are tested at VDDmin = 2.3 V. 4. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf =10 ns; VIL = VSS; VIH = VDD; XTAL2 not connected; EA = RST = Port 0 = VDD. 5. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; XTAL2 not connected; EA = Port 0 = VDD. 6. The Power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = Port 0 = VDD; RST = VSS. 7. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1.
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
f xtal (MHz)
14 12 10 8 6 4 2 0 0 2 4
MLA588 - 1
f xtal (MHz)
14 12 10 8 6 4 2 0
MGC441
VDD (V)
6
0
2
4
VDD (V)
6
Fig.33 Frequency operating range - P83CL781.
Fig.34 Frequency operating range - P83CL782.
24 I DD (mA) 18 12 MHz
MSA759 - 1
handbook, halfpage
8
MSA758
I DD(idle) (mA) 6
12 MHz
12 8 MHz
4 8 MHz
6
3.58 MHz
2 3.58 MHz
0 0 2 4 VDD (V) 6
0 0 2 4 VDD (V) 6
Tamb = 25 C. Oscillator option = Oscillator 3.
Tamb = 25 C. Oscillator option = Oscillator 3.
Fig.35 P83CL781: typical operating current as a function of frequency and VDD.
Fig.36 P83CL781: typical Idle current as a function of frequency and VDD.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
24 I DD (mA) 18 12 MHz
MLB166
8 I DD(idle) (mA) 6
MLB165
12 MHz
12 8 MHz
4
8 MHz 6 3.58 MHz 2
3.58 MHz 0 0 2 4 VDD (V) 6 0 0 2 4 VDD (V) 6
Tamb = 25 C. Oscillator option = Oscillator 3.
Tamb = 25 C. Oscillator option = Oscillator 3.
Fig.37 P83CL782: typical operating current as a function of frequency and VDD.
Fig.38 P83CL782: typical Idle current as a function of frequency and VDD.
handbook, halfpage
6
MSA756
I DD(pd) (A) 4
2
0 0 2 4 VDD (V) 6
Tamb = 25 C.
Fig.39 Typical Power-down current as a function of VDD.
1997 Mar 14
63
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
22 AC CHARACTERISTICS
P83CL781; P83CL782
The following AC characteristics apply to both the P83CL781 and P83CL782 unless otherwise stated. 22.1 Program memory VDD = 5 V; VSS = 0 V; Tamb = -40 to +85 C for the P83CL781 and -25 to +55 C for the P83CL782; CL = 50 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless specified. See Fig.40. SYMBOL tLL tAL tLA tLIV tLC tCC tCIV tCI tCIF tAC tAIV tAFC PARAMETER ALE pulse duration Address set-up time to ALE Address hold time after ALE Time from ALE to valid instruction input Time from ALE to control pulse PSEN Control pulse duration PSEN Time from PSEN to valid instruction input Input instruction hold time after PSEN Input instruction float delay after PSEN Address valid after PSEN Address to valid instruction input Address float delay after PSEN fosc = 12 MHz MIN. 127 43 48 - 58 215 - 0 - 75 - 12 MAX. - - - 233 - - 125 - 63 - 302 - fosc = VARIABLE MIN. 2tCK - 40 tCK - 40 tCK - 35 - tCK - 25 3tCK - 35 - 0 - tCK - 8 - 0 - - - 4tCK - 100 - - 3tCK - 125 - tCK - 20 - 5tCK - 115 - MAX. ns ns ns ns ns ns ns ns ns ns ns ns UNIT
handbook, full pagewidth
t CY t LL t LIV
ALE t LC t CC PSEN t LA t AL PORT 0 AD0 to AD7 t AFC t AIV PORT 2 address A8 to A15 address A8 to A15
MLA583
t CIV
t CIF instruction input t CI AD0 to AD7 instruction input
Fig.40 Read from Program Memory.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
22.2 External Data Memory VDD = 5 V; VSS = 0 V; Tamb = -40 to +85 C for P83CL781 and -25 to +55 C for the P83CL782; CL = 50 pF for Port 0, ALE and PSEN; CL = 40 pF for all other outputs unless specified. See note 1 and Figs 41 and 42. SYMBOL tRR tWW tLA tRD tDFR tLD tAD tLW tAW tWHLH tDWX tDW tWD tAFR Note 1. Interfacing the P83CL781 or the P83CL782 to devices with float times up to 75 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. RD pulse duration WR pulse duration Address hold time after ALE RD to valid data input Data float delay after RD Time from ALE to valid data input Address to valid data input Time from ALE to RD or WR Time from address to RD or WR Time from RD or WR HIGH to ALE HIGH Data valid to WR transition Data set-up time before WR Data hold time after WR Address float delay after RD PARAMETER fosc = 12 MHz MIN. 400 400 48 - - - - 200 203 43 23 433 33 - MAX. - - - 150 97 517 585 300 - 123 - - - 12 fosc = VARIABLE MIN. 6tCK - 100 6tCK - 100 tCK - 35 - - - - 3tCK - 50 4 tCK - 40 tCK - 60 7tCK - 150 tCK - 50 - - - - 5tCK - 165 2tCK - 70 8tCK - 150 9tCK - 165 3tCK + 50 - tCK + 40 - - - 12 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1997 Mar 14
65
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
t LD
P83CL781; P83CL782
handbook, full pagewidth
t WHLH
ALE
PSEN t LW RD t AL t LA t AW PORT 0 AD0 to AD7 t AFR t AD PORT 2 address A8 to A15 or Port 2 output
MLA584
t RR
t DFR t RD data input
Fig.41 Read from Data Memory.
t WHLH
handbook, full pagewidth
ALE
PSEN t LW t WW
WR t AW t AL t LA t DWX PORT 0 AD0 to AD7 data output t DW t WD
PORT 2
address A8 to A15 or Port 2 output
MLA585 - 1
Fig.42 Write to Data Memory.
1997 Mar 14
66
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
one machine cycle
one machine cycle S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2
1/1 page = 296 mm (Datasheet)
S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2
27 mm
dotted lines are valid when RD or WR are active
XTAL1 INPUT
ALE
only active during a read from external data memory only active during a write to external data memory
PSEN
RD
WR
external program memory fetch
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
inst. in
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
read or write of external data memory
BUS (PORT 0)
inst. in
address A0 - A7
inst. in
address A0 - A7
data output or data input
address A0 - A7
PORT 2
address A8 - A15
address A8 - A15 or Port 2 output
address A8 - A15
PORT 0, 2, 3 OUTPUT
old data
new data
PORT 1 OUTPUT
old data
new data
PORT 0, 2, 3 INPUT
sampling time of I/O port pins during input
SERIAL PORT CLOCK
MLA929
Fig.43 Instruction cycle timing.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
handbook, halfpage
0.7 VDD
0.7 VDD
0.9 VDD test points 0.4 VDD 0.3 VDD 0.3 VDD
MLA586
Fig.44 AC testing input waveform.
handbook, 4 columns 500 A
MSA763
I IL(T) II
100 A 0
I IL 0.5 VDD VDD
Fig.45 Input current.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
23 PACKAGE OUTLINES DIP40: plastic dual in-line package; 40 leads (600 mil)
P83CL781; P83CL782
SOT129-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 40 21 MH wM (e 1)
pin 1 index E
1
20
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.70 1.14 0.067 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 15.24 0.60
L 3.60 3.05 0.14 0.12
ME 15.80 15.24 0.62 0.60
MH 17.42 15.90 0.69 0.63
w 0.254 0.01
Z (1) max. 2.25 0.089
52.50 51.50 2.067 2.028
14.1 13.7 0.56 0.54
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT129-1 REFERENCES IEC 051G08 JEDEC MO-015AJ EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
1997 Mar 14
69
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L A A2 A1
Q (A 3) Lp
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 Q 1.2 0.9 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1997 Mar 14
70
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
P83CL781; P83CL782
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1997 Mar 14
71
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
24 SOLDERING 24.1 Introduction
P83CL781; P83CL782
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 C. 24.3.2 WAVE SOLDERING
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 24.2 24.2.1 DIP SOLDERING BY DIPPING OR BY WAVE
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 24.3.3 REPAIRING SOLDERED JOINTS
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 24.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 24.3 24.3.1 QFP REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). 1997 Mar 14 72
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
25 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
P83CL781; P83CL782
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 26 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 27 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Mar 14
73
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
NOTES
P83CL781; P83CL782
1997 Mar 14
74
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with UART and I2C-bus
NOTES
P83CL781; P83CL782
1997 Mar 14
75
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/1200/02/pp76
Date of release: 1997 Mar 14
Document order number:
9397 750 01511

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